1. Field of the Invention
The present invention relates generally to methods for the growth of single crystal material layer on a polycrystalline substrate.
2. Description of Related Art
A large area, inexpensive substrate for the growth of epitaxial layers (especially silicon carbide, SiC) has been a long-sought goal. Currently, single crystal 6H- or 4H-polytype SiC substrates are the predominantly used substrates for epitaxial SiC growth. However, single crystal SiC substrates are very expensive and are currently available in small substrates sizes of 2 inch diameter or less.
An alternate approach that has been investigated for SiC epitaxial growth on a large area substrate has been the growth of the cubic polytype of SiC (also referred to as the 3C or beta polytype of SiC) on a silicon substrate. The 3C polytype of SiC is desirable for its high electron mobility and high breakdown field for power electronic device applications, and its isotropic mobility characteristics for sensor applications. However, the large lattice mismatch (.about.20%) and thermal expansion mismatch (.about.8%) between SiC and silicon have to date prevented the growth of high quality SiC epitaxial layers on silicon substrates. An additional problem with this approach is that the optimum growth temperature for SiC epitaxial growth is between 1500.degree. C. and 1600.degree. C., well above the 1350.degree. C. maximum use and the 1450.degree. C. melting temperature of a silicon substrate.
Another approach for 3C--SiC growth on silicon substrate has been to first carbonize the silicon surface forming a thin 3C--SiC layer, and then to grow 3C--SiC epitaxial layers on the carbonized silicon surface at a growth temperature below 1350.degree. C. U.S. Pat. No. 4,855,254, issued to Eshita et al. describes a method to carbonize silicon substrate. There is a tendency for anti-phase domains to form in the epitaxial layer for 3C--SiC growth on a (100) orientation silicon substrate. U.S. Pat. No. 5,230,768, issued to Furukawa et al. and U.S. Pat. No. 5,279,701, issued to Shigeta, et. al. describes a method to to obtain improved growth of 3C--SiC material on a silicon substrate silicon substrate that is oriented miscut from (100) orientation. More recent studies have included the growth of 3C--SiC on silicon-on-insulator (SOI) substrates. U.S. Pat. No. 5,759,908, issued to Steckl et al. describes a method to fabricate SiC on SOI substrates.
It is sometimes possible to obtain polytype conversion in growth of SiC depending on the growth temperature, and thus hexagonal polytypes of SiC can sometimes be grown on a cubic polytype of SiC.
It is sometimes possible to obtain polytype conversion in growth of SiC depending on the growth temperature, and thus hexagonal polytypes of SiC can sometimes be grown on a cubic polytype of SiC for high temperature growth.
Wide bandgap gallium nitride (GaN) material has recently been demonstrated to be very beneficial for microwave power transistor applications, and for blue-green laser and light emitting diodes (LED). GaN epitaxial layers have typically been grown on a sapphire substrate or on single crystal SiC substrates. There are continuing searches for new substrates for GaN growth. Sapphire is electrically insulating, a disadvantage for vertical current conducting optical emitters and power devices, and has relatively high thermal impedance which is a disadvantage for high power microwave devices. The best quality GaN epitaxial layers have been obtained for material grown on SiC substrates, however, single crystal SiC substrates are very expensive and are only available in small substrate sizes. GaN epitaxial growth on silicon substrates is recently being investigated as an approach to obtain GaN epitaxial growth on large area substrates. There is however, significant thermal expansion mismatch between GaN and silicon which leads to cracking of the epitaxial layer for thick GaN epitaxial layers. There is also a significant lattice mismatch between GaN lattice and silicon lattice which limits the quality of GaN epitaxial layers grown on a silicon substrate. In addition, the silicon substrate is not suitable for microwave applications because of microwave loss in the conducting silicon substrate.
For GaN growth on a silicon substrate, different poly-types of GaN have a tendency to form, depending on the orientation of silicon substrate. Typically cubic polytypes of GaN will form on a (100) orientation silicon substrate. Likewise, hexagonal polytypes of GaN will form on a (111) orientation silicon substrate. In some cases, a preferred method to grow GaN on silicon is to first form a thin layer of cubic-SiC forms on the silicon surface by carbonization prior to the growth of GaN. There is a relatively good lattice constant match between cubic-GaN and cubic-SiC. Care should be taken in the GaN growth process, to avoid the formation of silicon nitride on the silicon surface prior to the GaN growth.
Non-single crystal ceramic substrates can be designed to have optimized mechanical, thermal expansion, thermal conduction, or electrical conduction properties for particular applications. One polycrystalline ceramic substrate that has especially desirable properties is poly-SiC. Poly-SiC substrates are manufactured commercially in hot pressed sintered form, reaction bonded form, and chemical vapor deposited (CVD) form. The CVD poly-SiC substrates are available commercially in substrate sizes up to 200 mm diameter, with thermal impedance as high as 310 W/mK, electrical resistivity as high as 100,000 ohm-cm at room temperature, electrical impedance as low as 1 ohm-cm, maximum use temperature greater than 2000.degree. C., and excellent thermal expansion matching to single crystal cubic-SiC. Hot pressed sintered poly-SiC substrates are commercially available that have many of the above characteristics, but with electrical impedances as low as 0.1 ohm-cm. Ceramic AlN substrates are available commercially is substrate sizes to 100 mm square, with thermal impedances as high as 170 W/mK, electrical resistivity as high as 10.sup.-13 ohm-cm at room temperature, and excellent thermal expansion matching to single crystal GaN. Polycrystalline diamond has thermal conductivity as high as 1000 W/mK. Ceramic silicon nitride has good thermal expansion matching to silicon. Ceramic graphite substrates are available with electrical impedances as small as 0.001 ohm-cm at room temperature. AlSiC substrates are commercially available, and have good expansion matching to silicon. Mechanical, thermal, optical and electrical data on a large variety of ceramic substrate materials can be found on the National Institute of Standards WWW Version of the Structureal Ceramic web site for ceramics:
http://www.ceramics.nist.gov/srd/scd/scdquery.htm PA1 http://www.ceramics.nist.gov/srd/scd/Z00390.htm
A provisional patent application filed on Jun. 30, 1998 by Kub and Hobart discussed several techniques to make ultra-thin wafer bonded material layers.
One method of fabricating thin wafer bonded semiconductor layer involves bond-and-etch back (BESOI) technique. The BESOI technique involves bonding a wafer an etch stop layer to an oxidized silicon handle wafer, thinning the wafer that contain the etch stop layer using grinding, chemically etching to the etch stop layer, and then etching the etch stop layer. A key step in the BESOI process is the method of forming the etch stop layer. Heavily doped boron concentration (&gt;10.sup.20 cm.sup.-3) layer have been used as the etch stop layer. U.S. Pat. No. 5,540,785, issued to Dennard et al. describes a method to fabricate BESOI that uses a heavily boron doped etch stop layer that has a small percentage of germanium added to heavily boron doped etch stop layer to produce a defect free epitaxial layer. U.S. Pat. No. 5,013,681 issued to Godbey et al. describes a method to fabricate BESOI that uses a strained SiGe etch stop. U.S. Pat. No. 5,024,723 issued to Goesele et al. describes a method to fabricate BESOI by implanting carbon ion into a substrate to form an etch stop layer. The disadvantage of all the BESOI approach is that the entire host substrate must be removed by a laborious sequence of grinding, polishing, and etching. In addition, overall thickness uniformity during the substrate thinning process must be critically maintained since the etch selectivity of Si over SiGe is limited (&lt;100).
U.S. Pat. No. 5,374,564 issued to Bruel describes another method of fabricating a thin wafer bonded semiconductor layer involving combining wafer bonding with a hydrogen implantation and separation technique. The hydrogen implantation and separation technique uses a heavy dose of implanted hydrogen together with subsequent annealing to produce H exfoliation that releases the host substrate to generate the SOI structure. Following exfoliation, the surface has a microroughness of about 8 nm, and must be given a slight chemomechanical polish to produce a prime surface. This step degrades the Si layer thickness uniformity and makes the process unsuitable for producing very thin Si films.
In the past, ultra-thin semiconductor layers have been produced by successive oxidation and oxide etching of silicon-on-insulator (SOI) wafers. In the oxide thinning technique, an SOI substrate with approximately a 200 nm thick silicon layer is thinned to approximately 50 nm by multiple oxidations and dilute hydrofluoric acid etches. This technique is heavily dependent on the thickness uniformity of the SOI silicon layer and the oxidation uniformity. SOI substrates often have a thickness non-uniformity of approximately 10 nm. Thus, the oxidation thinning technique is not suitable for manufacturing ultra-thin (&lt;10 nm) silicon layers.
Ultra-thin semiconductor layers are required for compliant substrates. In the compliant substrate approach, the ultra-thin semiconductor layer will be weakly bonded to a handle substrate and the thin compliant layer will expand or contract as a heteroepitaxially layer is grown on the surface of the ultra-thin semiconductor layer so that defects, if created, will reside in the ultra-thin semiconductor layer. In some cases, a potential mechanism for compliant operation is to bond a thin compliant material layer to a material that become viscous at a high growth temperature. Some examples of materials that become viscous at high temperature include silicon oxide at approximately 900.degree. C., germanium at 950.degree. C., and silicon at 1450.degree. C. In addition, metals, eutectics, and solders have a large range of melting temperatures ranging from 156.degree. C. for indium to greater than 1000.degree. C. for other metals. Glasses and oxides also have a wide range of melting temperatures ranging from below room temperature to greater than 1100 C. for fused quartz. In other cases, the thin compliant material layer can slip at the interface between the thin compliant material and the material layer that it is in contact with. The thin compliant layer will expand or contract during epitaxial layer growth and is susceptible to buckling of the thin compliant layer.
Direct wafer bonding typically requires polishing that the surfaces of the substrates to be bonded to a root mean square (RMS) surface roughness of less than 1 nm. Most materials can be polished to a surface roughness condition of less than 1 nm RMS. However, extensive polishing is required for some materials (e.g., silicon carbide and diamond) to achieve this surface roughness condition. There are a number of approaches that can be used to bond two substrates to reduce the requirement that the two substrate surfaces be polished to an RMS roughness of less than 1 nm. One approach is to deposit a material such as polysilicon, silicon dioxide, silicon nitride, or metal on the substrate surface, and then polish the material to a surface roughness of less than 1 nm RMS. The use of pressure, temperature, or vacuum separately or in combination also reduces the requirement to have a surface polishing of 1 nm or less. If one of the substrates is thin, then the thin substrate will more easily conform to the other substrate during bonding and thus reduce the requirement for surface roughness less than 1 nm RMS.
Metals can be deposited on the substrate surface and the metals will bond to the second substrate surface with the help of pressure, temperature, and vacuum possibly by forming a eutectic with the second substrate material. Metals can be deposited on both substrate surfaces and bonded. Brazing or soft solder materials can be deposited on one or both surfaces and the substrates bonded. Preceramic polymers can be used to bond two substrates. Ceramic materials can be deposited on one or both substrate surfaces, the substrates heated to the melting point of the ceramic material (sometimes under pressure, and the two substrates bonded. Materials such as silicon and germanium that melt during a bonding process and react with the substrate material can be used to bond two SiC substrates together. Electrostatic or anodic bonding can be used to bond a substrate to a alkali containing glass material. In some cases, alkali containing glass can be deposited on one surface by sputtering or evaporation and anodic bonding performed. A rough surface can be coated with a spin-on-glass to achieve a surface smooth enough for bonding. A low melting point frit or solder glass can be deposited on a surface and bonded to a second surface using pressure and temperature. A sodium silicate material deposited on a substrate surface will aid bonding. Bonding approaches that are appropriate for lower temperatures include polymer adhesive, organic adhesive, and epoxy bonding. The ambient is sometimes important during the bonding operation. For bonding of GaAs substrates, it is generally preferred to have a hydrogen ambient during bonding.